1. Field
The present disclosure generally relates to a semiconductor chip package. More specifically, the present disclosure relates to a chip package that includes a group of chips arranged in a stack, and a ramp component, which is oriented at an angle relative to the stack, and which is coupled to the chips.
2. Related Art
Chip packages that include stacked semiconductor chips can provide higher performance and lower cost in comparison to conventional individually packaged chips that are connected to a printed circuit board. These chip packages also provide certain advantages, such as the ability: to use different processes on different chips in the stack, to combine higher density logic and memory, and to transfer data using less power. For example, a stack of chips that implements a dynamic random access memory (DRAM) can use a high-metal-layer-count, high-performance logic process in a base chip to implement input/output (I/O) and controller functions, and a set of lower metal-layer-count, DRAM-specialized processed chips can be used for the rest of the stack. In this way the combined set of chips may have better performance and lower cost than: a single chip that includes I/O and controller functions manufactured using the DRAM process; a single chip that includes memory circuits manufactured using a logic process; and/or using a single process to make both logic and memory physical structures.
Existing techniques for stacking chips include wire bonding and through-silicon vias (TSVs). Wire bonding is a low-bandwidth, low-cost technique in which chips are stacked offset from one another to define a staircase of chip edges that includes exposed bond pads. Electrical connections to the chips are implemented by bonding wires to these bond pads.
In contrast, TSVs typically have a higher bandwidth than wire bonds. In a TSV fabrication technique, chips are processed so that one or more of their metal layers on their active face is conductively connected to new pads on their back face. Then, chips are adhesively connected in a stack, so that the new pads on the back face of one chip make conductive contact with corresponding pads on the active face of an adjacent chip.
However, TSVs typically have a higher cost than wire bonds. This is because TSVs pass through the active silicon layer of a chip. As a consequence, a TSV occupies area that could have been used for transistors or wiring. This opportunity cost can be large. For example, if the TSV exclusion or keep-out diameter is 20 μm, and TSVs are placed on a 30-μm pitch, then approximately 45% of the silicon area is consumed by the TSVs. This roughly doubles the cost per area for any circuits in the chips in the stack. (In fact, the overhead is likely to be even larger because circuits are typically spread out to accommodate TSVs, which wastes more area.) In addition, fabricating TSVs usually entails additional processing operations, which also increases the chip cost.
Hence, what is needed is a chip package that offers the advantages of stacked chips without the problems described above.